High speed digital systems, such as engineering workstations and personal computers, require clock sources to provide a timing reference. It is imperative that these timing references be highly accurate and stable. Otherwise, the performance of the digital systems relying on these clock sources would be impaired. One method for achieving a clean, fast, and accurate clock source is to use a crystal oscillator coupled with a phase-lock-loop (PLL) circuit to regulate its frequency. In this type of arrangement, the goal then is to design the PLL such that it exhibits low jitter and high bandwidth in order to generate an optimal clock signal.
The PLL circuitry in the clock generator typically contains a voltage controlled oscillator (VCO) that receives a voltage level maintained by filter components. Normally, charging currents and voltage controlled oscillator gains are so high that externally situated filter components are required to external, e.g., "off-chip," filter components (e.g., capacitors, etc.) increase the overall cost of the digital system in part by making manufacturing more complex, and also increase the physical size of the digital system. Furthermore, off-chip filter components also decrease system reliability by increasing the phase jitter by allowing external noise to be injected into the clock circuit through the PLL filter. Clock jitter is reduced if external elements of the PLL loop filter can be eliminated. To integrate filter components "on-chip," it is necessary to use smaller sized filter components. However, this leads to tighter filter leakage requirements because smaller sized capacitors are more sensitive to changes in current when compared to larger sized capacitors.
It is desired to reduce the effects of leakage current within a PLL circuit because, as discussed above, on-chip filter components are very sensitive to small leakage currents. PLL filters are normally driven by current source circuits and require outputs having a very high impedance. A problem exists in eliminating off-chip filters and placing them on-chip. Namely, reducing the size of the filters (thereby allowing them to be placed on-chip) unfortunately makes these components more sensitive to leakage current which impedes the ideal operation of certain PLL circuits. As a result, it is desired to use buffer circuits that have reduced leakage current to drive differential filters for higher PLL accuracy. At the same time, this circuitry needs to operate from increasingly lower power supply voltages, e.g., to accommodate hand-held and other portable battery operated applications. integrated on the same chip, which reduces cost and minimizes its susceptibility to external noise and other interferences, while also minimizing the effects of current leakage, thereby reducing clock jitter and maintaining tight PLL bandwidth requirements.